As is well known, a non-volatile memory is able to continuously retain data after the supplied power is interrupted. Generally, after the non-volatile memory leaves the factory, the user may program the non-volatile memory in order to record data into the non-volatile memory. According to the number of times the non-volatile memory is programmed, the non-volatile memory may be classified into a multi-time programming memory (also referred as a MTP memory) and a one time programming memory (also referred as an OTP memory). Basically, the stored data of the MTP memory can be modified many times. On the contrary, the OTP memory can be programmed once. After the OTP memory is programmed, the stored data fails to be modified.
For example, an OTP memory cell is disclosed in U.S. Pat. No. 6,920,067, which is entitled “Integrated circuit embedded with single-poly non-volatile memory”. FIG. 1A is a schematic top view of a conventional OTP memory cell. FIG. 1B is a schematic cross-sectional view of the conventional OTP memory cell of FIG. 1A. FIG. 10 is a schematic equivalent circuit diagram of the conventional OTP memory cell of FIG. 1A.
Please refer to FIGS. 1A˜1C. The conventional OTP memory cell 20 comprises two serially-connected p-type metal-oxide semiconductor (PMOS) transistors. The two PMOS transistors are constructed in an N-well region (NW). The N-well region NW is connected to an N-well voltage VNW. The first PMOS transistor is used as a floating gate transistor. The second PMOS transistor is used as a select transistor.
In the first PMOS transistor, a gate oxide layer 27 is formed over the N-well region NW, and a floating gate 26 is formed over the gate oxide layer 27. A p-type source/drain region 21 receives a bit line voltage VBL. Moreover, a p-type source/drain region 22 may be considered as a combination of a p-type source region of the first PMOS transistor and a p-type drain region of the second PMOS transistor.
In the second PMOS transistor, a gate oxide layer 25 is formed over the N-well region NW, and a select gate 24 is formed over the gate oxide layer 25. The select gate 24 receives a select gate voltage VSG. Moreover, a p-type source/drain region 23 receives a source line voltage VSL.
Generally, the p-type source/drain region 21 is connected with a bit line for receiving the bit line voltage VBL, the select gate 24 of the second PMOS transistor is connected with a word line for receiving the select gate voltage VSG, and the p-type source/drain region 23 is connected with a source line for receiving a source line voltage VSL. By properly controlling the select gate voltage VSG, the source line voltage VSL, the bit line voltage VBL and the N-well voltage VNW, the conventional OTP memory cell 20 may be operated in a program cycle or a read cycle.
In the conventional OTP memory cell 20, the floating gate transistor with two gate structure in the early stage is modified as the floating gate transistor with single gate structure. That is, the floating gate transistor in the early stage has the floating gate and the control gate. Whereas, the conventional OTP memory cell 20 has a single floating gate but does not have the control gate. Since the two PMOS transistors of the conventional OTP memory cell 20 have respective gates 24 and 26, the process of fabricating the conventional OTP memory cell 20 is compatible with the standard CMOS manufacturing process.
Nowadays, the CMOS manufacturing process is selected according to the operating voltage range of the semiconductor device. For example, the CMOS manufacturing process for a medium voltage device (MV device) is used to fabricate a transistor with higher voltage stress, and this transistor is suitable for the medium voltage operation. In addition, the CMOS manufacturing process for a low voltage device is used to fabricate a transistor with fast computing speed and lower voltage stress, and this transistor is suitable for the low voltage operation. For example, in the medium voltage operation, the voltage stress that can be withstood by the region between the gate terminal and the source terminal of the transistor is in the range between 3.0V and 6.5V. Moreover, in the low voltage operation, the voltage stress that can be withstood by the region between the gate terminal and the source terminal of the transistor is in the range between 1.8V and 2.0V.
Generally, an integrated circuit comprises an input/output device (I/O device) and a core device. The I/O device can withstand high voltage stress. The core device is operated at a high speed. That is, in the manufacturing process of an integrated circuit, the medium voltage device manufacturing process is needed to fabricate the I/O device and the low voltage device manufacturing process is needed to fabricate the core device.
Moreover, during the program cycle of the conventional OTP memory cell, the voltage difference between the gate terminal and the source terminal is about 6V. In other words, the two PMOS transistors of the OTP memory cell 20 as shown in FIG. 1B are medium voltage devices. For operating the OTP memory cell 20 in a low voltage condition, it is necessary to modify the structure of the OTP memory cell 20.
FIG. 2 is a schematic equivalent circuit diagram of another conventional OTP memory cell. As shown in FIG. 2, the OTP memory cell 30 comprises a word line driver 32 and a storage unit 34. Similarly, both of the two serially-connected PMOS transistors of the storage unit 34 are medium voltage devices. The structures of the storage unit 34 is identical to the OTP memory cell 20 of FIG. 10, and are not redundantly described herein.
The OTP memory cell 30 is in the low voltage operation. For controlling the second PMOS transistor (i.e., the select transistor), the OTP memory cell 30 uses the word line driver 32 to increase the lower word line voltage VWL to the select gate voltage VSG. Consequently, the second PMOS transistor (i.e., the select transistor), the OTP memory cell 30 can be normally operated. An example of the word line driver 32 is a level shifter.
Since the OTP memory cell 30 is additionally equipped with the word line driver 32, a great amount of electric energy is consumed during the read cycle or the program cycle.